Semiconductor wafer package and manufacturing method thereof

ABSTRACT

A manufacturing method of a semiconductor wafer package mainly comprises the following steps. Firstly, a semiconductor wafer having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, under bump metallurgy layers are formed on each of the bonding pads respectively. Then, a mask is formed above the semiconductor wafer to expose the under bump metallurgy layers through each of the openings of the mask. Afterwards, a plurality of bump structures are disposed separately in the openings wherein each of the bump structures has a bump and a reinforced layer covering the bump. Finally, a reflow step is performed so that each of the reflowed bumps is connected to the corresponding under bump metallurgy layer and the reinforced layers are transformed into bump-reinforced collars to cover the under bump metallurgy layers and encompass the bumps. In addition, a semiconductor wafer package, which is formed by the manufacturing method, is provided.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to a semiconductor wafer package. Moreparticularly, the present invention is related to a semiconductor waferpackage having a plurality of solder bumps encompassed by a plurality ofbump-reinforced collars respectively and the manufacturing methodthereof.

2. Related Art

In this information explosion age, integrated circuits products are usedalmost everywhere in our daily life. As fabricating technique continueto improve, electronic products having powerful functions, personalizedperformance and a higher degree of complexity are produced. Nowadays,most electronic products are relatively light and have a compact body.Hence, in semiconductor production, various types of high-densitysemiconductor packages, for example ball grid array package (BGA),chip-scale package (CSP), multi-chips module package (MCM) and flip chippackage (F/C), have been developed.

However, as mentioned above, flip chip is one of the most commonly usedtechniques for forming an integrated circuits package. Compared with awire-bonding package or a tape automated bonding (TAB) package, aflip-chip package has a shorter electrical path on average and has abetter overall electrical performance. In said flip-chip package, thebonding pads on a chip and the contacts on a substrate are connectedtogether through a plurality of bumps formed by the method of bumpingprocess. It should be noted that there is further an under bumpmetallurgy layer disposed on the bonding pads of the chip to be regardedas a connection medium for connecting to the bumps and enhancing themechanical strength of the connection of the chip to the substrate aftersaid chip is attached to the substrate.

Moreover, said manufacturing method of a semiconductor wafer package isusually utilized in flip chip technology. Therein, a plurality of underbump metallurgy layers are formed on the corresponding bonding pads ofthe wafer respectively, and a plurality of solder balls or bumps aremounted onto the under bump metallurgy layers so as to be regarded asinterconnections for electrically and mechanically connecting the chipand the substrate when the chip is flip-chip bonded to the substrate.

Referring to FIG. 1, it illustrates a partially cross-sectional view ofa conventional semiconductor wafer 100. Therein, the semiconductor wafer100 has a plurality of bonding pads 102 and a passivation layer 104exposing the bonding pads 102. Moreover, under bump metallurgy layers106 are formed on the bonding pads 102 respectively. After asemiconductor wafer 100 as shown above is provided, a plurality ofreinforced layers 108 are formed on the under bump metallurgy layers106, preferably, said reinforced layers 108 are located over the bondingpads 102. Afterwards, a plurality of solder bumps or solder balls 109are disposed on the reinforced layers 108. Generally speaking, thereinforced layers are made of a material comprising polyimide,Benzocyclobutene (BCB) and polymer materials.

Next, referring to FIG. 1 again and FIG. 2, when the solder bumps 109are performed a reflow process, the reflowed solder bumps 110 aresecurely attached to the under bump metallurgy layers 106 and saidreinforced layers 108 are melted to be transformed into a plurality ofbump-reinforced collars 112 to cover the periphery of each solder bumps110 as shown in FIG. 2.

In general, each of the under bump metallurgy layers 106 mainlycomprises an adhesive layer, a barrier layer and a wetting layer. Theadhesive layer is utilized to enhance the mechanical strength of theconnection of the bonding pad 102 to the barrier layer, wherein thematerial of the adhesive layer is made of aluminum or titanium. Thebarrier layer is utilized to avoid the diffusion of the underlyingmetal, wherein the material of the barrier layer usually includesnickel-vanadium alloy, nickel-copper alloy and nickel. In addition, thewetting layer, for example a copper layer, is utilized to enhance thewettability of the solder bump 109 with the under bump metallurgy layer106. It should be noted that the under bump metallurgy layers 106 areformed through the processes of placing photo-resist, proceeding platingor sputtering metal on the surface of the semiconductor wafer 100 andetching the metal.

As mentioned above, there is needed the bump-reinforced collar 112 witha thickness not less than first-six of the diameter or the height of thereflowed solder bump 110 to well cover the reflowed solder bump 110 andenhance the mechanical reliability of the reflowed solder bump 110. Tobe noted, each of the reinforced layers 108 is disposed on thecorresponding bonding pad 102 through printing process by usingphoto-mask and stencil, accordingly, said reinforced layer 108 is notwell and equally distributed on the under bump metallurgy layer 106.Moreover, the solder bumps 109 are directly placed on the reinforcedlayers 108 before the bumps 109 are reflowed; and then the reinforcedlayers 108 are melted to be transformed into bump-reinforced collars 112to partially cover and encompass the reflowed solder bumps 110 to havethe reflowed solder bumps 110 securely attached to the under bumpmetallurgy layers 106 by penetrating the reinforced layers 108 afterreflowing the solder bumps 110. Thus, the portion of each of thereflowed solder bumps 110 not covered by the bump-reinforced collar 112is not substantially the same with each other. Namely, the height ofeach reflowed solder bump 110 encompassed by the reinforced collar 112is not substantially the same with each other, for example H1 isdifferent from H2 as shown in FIG. 2.

Per the above disadvantages, it will lower the mechanical reliability ofthe semiconductor wafer package and the combination of said chip of thesemiconductor wafer package and substrate. Therefore, providing anothermethod for forming bumps to solve the mentioned-above disadvantages isthe most important task in this invention.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, this invention is to provide asemiconductor wafer package having a plurality of reflowed bumps whichare covered by the bump-reinforced collars respectively and themanufacturing method thereof.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides a manufacturing method of a semiconductor waferpackage mainly comprising the following steps. Firstly, a semiconductorwafer is provided, wherein the semiconductor wafer has a plurality ofbonding pads, a plurality of under bump metallurgy layers and apassivation layer exposing the under bump metallurgy layers located overthe bonding pads. Next, a mask, such as a photo-resist layer or aphoto-mask, is provided to cover the active surface of the semiconductorwafer and form a plurality of openings to expose the under bumpmetallurgy layers located over the bonding pads. Afterwards, a pluralityof solder-bump structures are placed in the openings. To be noted, eachsolder-bump structure comprises a solder bump and a reinforced layercovering the solder bump. Finally, a reflow process is performed to meltthe solder-bump structures to have the solder bumps transformed intoreflowed solder bumps and attached to the under bump metallurgy layersand have the reinforced layer transformed into bump-reinforced collarsto cover the reflowed solder bumps and the under bump metallurgy layers.And then the mask is removed to complete the semiconductor wafer packageprocess to form a semiconductor wafer package.

Moreover, the invention also provides a semiconductor wafer packageaccording to the above manufacturing method. Therein, the semiconductorwafer package mainly comprises a semiconductor wafer, a plurality ofreflowed solder bumps disposed on the semiconductor wafer and aplurality of bump-reinforced collars covering the reflowed solder bumps,respectively, to at least expose the top of the reflowed solder bumps.Said semiconductor wafer has an active surface, a passivation layerlocated on the active surface, a plurality of bonding pads exposed outof the passiveation layer and a plurality of under bump metallurgylayers disposed on the bonding pads. In addition, the height of theportion of each reflowed solder bump not covered by the bump-reinforcedcollar is substantially the same with each other.

As mentioned above, the reinforced layer formed on and covering eachsolder bump to form a solder-bump structure is a thin reinforced layer,and said reinforced layer is well and equally distributed on each solderbump. Accordingly, when the solder-bump structures are reflowed to havethe reinforced layer melted, there will be no melted reinforced layerdisposed on the under bump metallurgy layers so as to easily transformthe reinforced layer into a plurality of bump-reinforced collars to wellcover the reflowed solder bumps. Thus, the height of the portion of eachreflowed solder bump covered by the bump-reinforced collar 210 issubstantially the same with each other, for example H3 and H4 as shownin FIG. 3 are substantially the same with each other, after said reflowprocess is performed.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will become more fully understood from the detaileddescription given herein below illustrations only, and thus are notlimitative of the present invention, and wherein:

FIG. 1 and FIG. 2 are partially enlarged cross-sectional views showingthe progression of steps for forming a conventional semiconductor waferpackage;

FIG. 3 illustrates a partially cross-sectional view of the semiconductorwafer package according to the preferred embodiment; and

FIGS. 4 to 7 are partially enlarged cross-sectional views showing theprogression of steps for forming a semiconductor wafer package accordingto the preferred embodiment of this invention.

DETAILED DESCRIPTION OF THE INVENTION

The semiconductor wafer package according to the preferred embodiment ofthis invention will be described herein below with reference to theaccompanying drawings, wherein the same reference numbers are used inthe drawings and the description to refer to the same or like parts.

FIG. 3 is partially enlarged cross-sectional views showing thesemiconductor wafer package according to the preferred embodiment.

Referring to FIG. 3 again, it shows the partially enlargedcross-sectional view of the semiconductor wafer 200. Therein, thesemiconductor wafer 200 has bonding pads 202, a passivation layer 204exposing the bonding pads 202 and a plurality of under bump metallurgylayers 206 formed on the bonding pads 202. Furthermore, a plurality ofreflowed solder bumps 208 are formed on the under bump metallurgy layers206. To be noted, the passivation layer 204 is provided to protect theactive surface of the semiconductor wafer 200. Moreover, the reflowedsolder bumps 208 are covered or encompassed by bump-reinforced collars210. Therein, the top of each reflowed solder bump 208 is at leastexposed out of the bump-reinforced collar 210. Generally speaking, theheight of the portion of each reflowed solder bump 208 covering thebump-reinforced collar 210 shall not be more than fifth-six of theheight of the reflowed solder bump 208. To be noted, the reinforcedlayer is a thin layer and is initially formed on and covers the solderbump to form solder-bump structure, the reinforced layer is welldistributed on each solder bump. Accordingly, when the solder-bumpstructures with reinforced layer thereon are reflowed, thebump-reinforced collars transforming from the reinforced layers willwell and equally distributed at the periphery of the correspondingreflowed solder bumps 208 to have the height of the portion of eachreflowed solder bump 208 covered by the bump-reinforced collar 210 besubstantially the same with each other.

Besides, each of the under bump metallurgy layers 206 generallycomprises an adhesive layer, a barrier layer and a wetting layer. Theadhesive layer is utilized to enhance the mechanical strength of theconnection of the bonding pad 202 to the barrier layer, wherein thematerial of the adhesive layer is made of aluminum or titanium. Thebarrier layer is utilized to avoid the diffusion of the underlyingmetal, wherein the material of the barrier layer usually includesnickel-vanadium alloy, nickel-copper alloy and nickel. In addition, thewetting layer, for example a copper layer, is utilized to enhance thewettability of the reflowed solder bump 208 with the under bumpmetallurgy layer 206. It should be noted that the under bump metallurgylayers 206 are formed through the processes of placing photo-resist,proceeding plating or sputtering metal on the surface of thesemiconductor wafer 200 and etching the metal

Next, referring to the drawings shown from FIG. 4 to FIG. 7, thesedrawings illustrate partially enlarged cross-sectional views showing theprogression of steps for forming a semiconductor wafer package accordingto the preferred embodiment of this invention.

Firstly, referring to FIG. 4, a semiconductor wafer 300 is provided,wherein the semiconductor wafer 300 has a plurality of bonding pads 302and a passivation layer 304 disposed above the active surface of thesemiconductor wafer 300 and exposing the bonding pads 302.

Next, referring to FIG. 5, under bump metallurgy layers 306 are formedover the active surface of the semiconductor wafer 300 to cover thebonding pads 302. Moreover, a mask 307 is formed above the semiconductorwafer 300 to form a plurality of openings 307 a to expose the under bumpmetallurgy layers 306. Therein, the openings 307 expose the under bumpmetallurgy layers 306 located over the bonding pads 302. Then, aplurality of solder-bump structures 308 are disposed in the openings 307a. To be noted, each solder-bump structure 308 is made of a solder bump308 a and a reinforced layer 308 b covering the solder bump 308 a.

As mentioned above, referring to FIG. 5 again and FIG. 6, a reflowprocess is performed to melt the solder-bump structures 308 to have thereinforced layers 308 b to be transformed into bump-reinforced collars310 and have the solder bumps 308 a melted into reflowed solder bumps309 to be securely attached to the under bump metallurgy layers 306. Tobe noted, the bump-reinforced collars are made of a polymer material andcover the solder bumps 309 with a height of no more than first-six ofthe height of the reflowed solder bumps 309 to enhance the mechanicalstrength of the attachment of the reflowed solder bumps 309 to the underbump metallurgy layers 306.

Besides, the reinforced layer 308 b covering the surface of the solderbump 308 a is thin so that that the reinforced layer 308 b isdistributed well and equally on the surface of the solder bump 308 a. Insuch a manner, when the reinforced layer 308 b is melted to betransformed into the bump-reinforced collar 310 to cover the relowedsolder bump 309, the height of the portion of the reflowed solder bump309 is substantially the same with the others. Namely, the heights of H5and H6 as shown in FIG. 7 are substantially the same with each other.

To be continued and as specified in the above, when the under bumpmetallurgy layer is extended over the passivation layer to be regardedas a redistributed layer and a redistributed pad, said above-mentionedmethod shall also apply to the semiconductor wafer having redistributedlayers and redistributed pads.

As mentioned above, the reinforced layer formed on and covering eachsolder bump as a solder-bump structure is a thin reinforced layer andsaid reinforced layer is well and equally distributed on each solderbump. Accordingly, when the solder-bump structures are reflowed to havethe reinforced layer melted, there will be no melted reinforced layerdisposed on the under bump metallurgy layers so as to easily transformthe reinforced layer into a plurality of bump-reinforced collars to wellcover the reflowed solder bumps. Thus, the height of the portion of eachsolder bump covered by the reinforced layer is substantially the samewith each other, after said reflow process is performed.

Although the invention has been described in considerable detail withreference to certain preferred embodiments, it will be appreciated andunderstood that various changes and modifications may be made withoutdeparting from the spirit and scope of the invention as defined in theappended claims.

1-9. (canceled)
 10. A semiconductor wafer package, comprising: asemiconductor wafer having an active surface, a plurality of bondingpads formed on the active surface, a passivation layer located above thesemiconductor wafer and exposing the bonding pads and a plurality ofunder bump metallurgy layers formed on the bonding pads; a plurality ofreflowed bumps disposed on the under bump metallurgy layers; and aplurality of bump-reinforced collars, the bump-reinforced collarsencompassing the reflowed bumps and covering the under bump metallurgylayers, wherein each of the reflowed bumps is exposed out of the eachbump-reinforced collar having an exposed portion with a heightsubstantially the same with each other.
 11. The semiconductor waferpackage of claim 10, wherein the reflowed bump is a solder bump.
 12. Thesemiconductor wafer package of claim 10, wherein the bump-reinforcedcollar is made of a polymer material.
 13. The semiconductor waferpackage of claim 10, wherein the passivation layer is made of a materialselected from silicon nitride, phosphosilicate glass and silicon oxide.14. The semiconductor wafer package of claim 10, wherein each of theunder bump metallurgy layers comprises a titanium layer, anickel-vanadium layer and a copper layer.
 15. The semiconductor waferpackage of claim 10, wherein the height of the exposed portion of thereflowed bump is at least equal to the first-six of the height of thereflowed bump.
 16. The semiconductor wafer package of claim 10, whereinthe height of the exposed portion of reflowed bumps is more than thefirst-six of the height of the reflowed bump.
 17. The semiconductorwafer package of claim 10, wherein said each reflowed bump is a goldbump.
 18. The semiconductor wafer package of claim 10, wherein each ofthe under bump metallurgy layers is made of a material selected fromtitanium, titanium-tungsten alloy, aluminum, aluminum-nickel,nickel-vanadium, chromium-copper alloy, copper and nickel-vanadium. 19.The semiconductor wafer package of claim 10, wherein the reflowed bumpsare located over the bonding pads.
 20. The semiconductor wafer packageof claim 10, wherein one of the under bump metallurgy layers is extendedover the active surface of the semiconductor wafer.